This invention is directed toward the field of integrated logic gates. More specifically, the present invention is a structure for an integrated injection logic (I.sup.2 L) Gate which provides a reduced leakage current in a high temperature, high voltage application, along with increased gate current gain and a method for producing such a structure.
I.sup.2 L gates are useful where a dense concentration of circuits is required on a chip, due to the compact size of each gate. However, I.sup.2 L gates have been plagued by problems such as low current gain (.beta.) and power loss in the lateral transistor when implemented in high temperature, high voltage, bipolar processes. Current loss occurs at the silicon-silicon dioxide interface due to the presence of interface traps which attract the holes and electrons and causes recombination. The area of this recombination zone is dependent upon doping concentration and temperature. Current loss between the emitter and collector of a transistor affects the transistor's .beta..
One attempted solution to reduce power loss in I.sup.2 L gates is the device disclosed in U.S. Pat. No. 4,260,988 issued to Russell. This patent discloses an I.sup.2 L gate with a double diffused injector transistor which can be configured with a high resistance region between its base and ground as shown in FIGS. 6B and 6C of the cited patent. This additional resistance, it is claimed, reduces parasitic leakage in the injector transistor. However, the double diffused injector and the use of the common substrate as the emitter of the vertical output transistor are incompatible with a high voltage, analog-digital bipolar process having lightly doped epitaxial and substrate.